1. Field of the Invention
The present invention relates to a shift register with a lower coupling effect. More particularly, the present invention relates to a LCD having shift registers with lower coupling effect.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a conventional LCD 100. The LCD 100 comprises a pixel circuit 110, a shift register area 120. The pixel circuit 110 comprises a plurality of pixels 111. The shift register area 120 comprises a plurality of shift registers S1-Sn for receiving the external voltage level signal VSS, the clock signal XCK, the clock signal CK, and a start signal ST and for transmitting gate driving signals G1-Gn to the pixel circuit 110 according to the received signals. The pixel circuit 110 respectively drives the pixels 111 according to the gate driving signals G1-Gn for displaying.
FIG. 2 is a diagram illustrating the shift register area 120 of the conventional LCD 100. As shown in FIG. 2, all of the shift registers S1-Sn receives the voltage level signal VSS, the clock signal XCK, and the clock signal CK. The first shift register S1 receives the start signal ST, and transmits the first gate driving signal G1 to the pixel circuit 110 and the second shift register S2 after a predetermined period according to the signals VSS, XCK, and CK. The second shift register S2 receives the first gate driving signal G1, and transmits the second gate driving signal G2 to the pixel circuit 110 and the third shift register S3 after the predetermined period, and so on. Thus, each shift register of the shift register area 120 sequentially transmit gate driving signals to drive the pixels 111 of the pixel circuit 110.
FIG. 3 is a diagram illustrating the signals of the conventional shift register area 120. As shown in FIG. 3, when the first shift register S1 receives the start signal ST, the shift register area 120 is triggered to sequentially generate the gate driving signal G1, and then G2, and so on. In this way, the pixels 111 of the pixel circuit 110 are sequentially driven for displaying.
FIG. 4 is a block diagram illustrating a conventional shift register 400. The shift register 400 comprises seven switches Q1-Q7, 3 control circuits 410-430, and an output circuit 440. The output circuit 440 comprises a switch Q8. The control circuit 410 respectively controls the voltages of the nodes B and C through the switches Q2 and Q3 according to the clock signal CK. When the control circuit 410 turns on the switches Q2 and Q3 according to the clock signal CK, the voltages of the nodes B and C are pulled to the voltage level VSS. The control circuit 420 respectively controls the voltages of the nodes B and C through the switches Q4 and Q5 according to the clock signal XCK. When the control circuit 420 turns on the switches Q4 and Q5 according to the clock signal XCK, the voltages of the nodes B and C are pulled to the voltage level VSS. The control circuit 430 respectively controls the voltages of the nodes B and C through the switches Q6 and Q7 according to the gate driving signal Gn+1 of the next stage. When the control circuit 430 turns on the switches Q6 and Q7 according to the gate driving signal Gn+1 of the next stage, the voltages of the nodes B and C are pulled to the voltage level VSS. The output circuit 440 transmits the clock signal CK to the node C for generating the gate driving signal Gn according to the voltages of the nodes B and C. In this way, when the gate driving signal Gn−1 of the previous stage inputs the shift register 400, the shift register 400 operates the way shown in FIG. 3, delays a predetermined period, and then outputs the gate driving signal Gn.
FIG. 5 is a diagram illustrating a gate driving signal Gn of the conventional shift register. Because an intrinsic capacitor C1 of the switch Q8 exists between the nodes B and A which enables the current to flow from the node A to the node B, this interferes with the switch Q8 and causes the switch Q8 to turn off incompletely and still pass unwanted signals. In other words, when the switch Q8 is turned-off, parts of the clock signal CK still pass to the node C and affects the gate driving signal Gn. The condition described above gets worse as the switch Q8 becomes old. Thus, the gate driving signal gets worse and the quality of the display is deteriorated.